The invention relates to electrical packages and processes for assembly and mounting thereof. More particularly, the invention relates to leaded packages providing large numbers of pin connections and processes for assembly and mounting thereof.
Pin grid array packages, such as multilayer co-fired alumina ceramic pin grid arrays typically have been produced by molybdenum or tungsten metalization of unfired cast alumina. An attach recess is provided in the upper layer and holes are punched in the green alumina to allow inter-level metalization. The green alumina is then fired. Pins are welded to the metalization on the bottom of the package providing electrical contact points protruding from the package. A semiconductor chip is placed in the attach recess, adhesive bonded into place, and wire bonded to the metalization. Finally, a protective cover is placed over the semiconductor chip and the package is sealed.
Printed circuit versions of pin grid array packages incorporate typical printed circuit laminates (epoxy/glass and polyimide/glass) with etched copper conductors. One approach involves a construction very similar to that employed in the conventional ceramic package with multiple circuit layers providing space for conductors, a die attach area (recessed), and pin connections. Rather than being welded, the pins typically are press-fit into plated-though holes and are sometimes soldered as well. The semiconductor chip is adhesive bonded into the recess and connected to the etched conductors by wire bonding.
An alternate printed circuit package structure involves a single-layer construction with holes and pins soldered therein. An attach recess is formed by machining a recess in the substrate to the desired depth. This approach reduces material costs but the depth and flatness of the machined attach recess are difficult to control and can result in excess stress on the wire bonds.
U.S. Pat. No. 4,074,342 to Honn et al describes a non-wire-bonded method where the semiconductor chip is "flip chip" mounted. The pin grid array is mounted in a plastic substrate whose thermal expansion is restrained. In the preferred embodiment, the semiconductor chip is not directly connected to the pin grid array but rather a circuit transposer is placed between them. The circuit transposer comprises a semiconductor material with conductors thereon that link the attached semiconductor chip to the pin grid array. This configuration eliminates mechanical stress on the solder joints which would otherwise occur from thermal coefficient of expansion mismatch between packaging materials. While this eliminates some of the thermal limitations of pin grid array packages, it is considerably more complex to produce. In one embodiment of Honn et al, the pins are extended at 1/2 inch (13 mm) before engaging the circuit transposer in order to accommodate mechanical stresses and the through connections in the transposer are etched to provide a small socket which facilitates positioning of the engaging pin and enhances the mechanical stress resistance.
In yet another embodiment, Honn et al dispenses with the transposer and forms a metallic conductive pattern directly on the plastic base to connect the pins to the flip chip. In both approaches, the processing of the component after the pins are in place can adversely affect the dimensional stability of the pin grid array.
While these alternative approaches represent some improvement, they are still cumbersome to produce and assemble and present limitations in terms of mechanical, electrical, and thermal characteristics of the completed pin grid array package.